The present invention relates generally to fabrication of field effect transistors having scaled-down dimensions, and more particularly, to fabrication of a field effect transistor using a semiconductor material having multiple thicknesses in SOI (semiconductor on insulator) technology, for minimizing short-channel effects in the field effect transistor and for minimizing series resistance at the drain and source.
Referring to FIG. 1, a common component of a monolithic IC is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 100 which is fabricated within a semiconductor substrate 102. The scaled down MOSFET 100 having submicron or nanometer dimensions includes a drain extension junction 104 and a source extension junction 106 formed within an active device area 126 of the semiconductor substrate 102. The drain extension junction 104 and the source extension junction 106 are shallow junctions to minimize short-channel effects in the MOSFET 100 having submicron or nanometer dimensions, as known to one of ordinary skill in the art of integrated circuit fabrication.
The MOSFET 100 further includes a drain contact junction 108 with a drain silicide 110 for providing contact to the drain of the MOSFET 100 and includes a source contact junction 112 with a source silicide 114 for providing contact to the source of the MOSFET 100. The drain contact junction 108 and the source contact junction 112 are fabricated as deeper junctions such that a relatively large size of the drain silicide 110 and the source silicide 114 respectively may be fabricated therein to provide low resistance contact to the drain and the source respectively of the MOSFET 100.
The MOSFET 100 further includes a gate dielectric 116 and a gate electrode 118 which may be comprised of polysilicon. A gate silicide 120 is formed on the polysilicon gate electrode 118 for providing contact to the gate of the MOSFET 100. The MOSFET 100 is electrically isolated from other integrated circuit devices within the semiconductor substrate 102 by shallow trench isolation structures 121. The shallow trench isolation structures 121 define the active device area 126, within the semiconductor substrate 102, where a MOSFET is fabricated therein.
The MOSFET 100 also includes a spacer 122 disposed on the sidewalls of the gate electrode 118 and the gate dielectric 116. When the spacer 122 is comprised of silicon nitride (Si3N4), then a spacer liner oxide 124 is deposited as a buffer layer between the spacer 122 and the sidewalls of the gate electrode 118 and the gate dielectric 116.
A long-recognized important objective in the constant advancement of monolithic IC (Integrated Circuit) technology is the scaling-down of IC dimensions. Such scaling-down of IC dimensions reduces area capacitance and is critical to obtaining higher speed performance of integrated circuits. Moreover, reducing the area of an IC die leads to higher yield in IC fabrication. Such advantages are a driving force to constantly scale down IC dimensions.
As the dimensions of the MOSFET 100 are scaled down further, the junction capacitances formed by the drain and source extension junctions 104 and 106 and by the drain and source contact junctions 108 and 112 may limit the speed performance of the MOSFET 100. Thus, referring to FIG. 2, a MOSFET 150 is formed with SOI (semiconductor on insulator) technology. In that case, a layer of buried insulating material 152 is formed on the semiconductor substrate 102, and a layer of semiconductor material 154 is formed on the layer of buried insulating material 152. A drain region 156 and a source region 158 of the MOSFET 150 are formed in the layer of semiconductor material 154. Elements such as the gate dielectric 116 and the gate electrode 118 having the same reference number in FIGS. 1 and 2 refer to elements having similar structure and function. Processes for formation of such elements 116, 118, 152, 154, 156, and 158 of the MOSFET 150 are known to one of ordinary skill in the art of integrated circuit fabrication.
In FIG. 2, the drain region 156 and the source region 158 are formed to extend down to contact the layer of buried insulating material 152. Thus, because the drain region 156, the source region 158, and a channel region 160 of the MOSFET 150 do not form a junction with the semiconductor substrate 102, junction capacitance is minimized for the MOSFET 150 to enhance the speed performance of the MOSFET 150 formed with SOI (semiconductor on insulator) technology, as known to one of ordinary skill in the art of integrated circuit fabrication.
The layer of semiconductor material 154 on the buried insulating material 152 is formed to be relatively thin (having a thickness of about 50 angstroms to about 500 angstroms for example) such that the channel region 160 between the drain and source regions 156 and 158 is filly depleted during operation of the MOSFET 150. Operation of the MOSFET 150 formed in SOI (semiconductor on insulator) technology with the fully depleted channel region 160 to minimize undesired short channel effects is known to one of ordinary skill in the art of integrated circuit fabrication.
However, because the layer of semiconductor material 154 is formed to be relatively thin for the fully depleted channel region 160 of the MOSFET 150, the drain and source silicides formed with the drain and source regions 156 and 158 are confined to be relatively thin. Relatively thin drain and source silicides disadvantageously result in higher parasitic resistance at the drain and source of the MOSFET 150 to degrade the speed performance of the MOSFET 150. Nevertheless, a relatively thin layer of semiconductor material 154 is used for the fully depleted channel region 160 to minimize undesired short channel effects of the MOSFET 150.
Thus, a mechanism is desired for using a relatively thin semiconductor material to form the drain and source regions and the channel region of the field effect transistor to minimize undesired short channel effects while forming drain and source silicides with a thicker semiconductor material to minimize parasitic resistance at the drain and source.
Accordingly, in a general aspect of the present invention, a field effect transistor is fabricated by forming a semiconductor material having portions with multiple thicknesses in SOI (semiconductor on insulator) technology, to form drain and source extension junctions on a thinner portion of the semiconductor material and to form drain and source silicides on a thicker portion of the semiconductor material.
In one embodiment of the present invention, in a method for fabricating a field effect transistor on a buried insulating material in SOI (semiconductor on insulator) technology, a layer of dielectric material is deposited on the buried insulating material. The layer of dielectric material is patterned to form a dielectric island having a top surface and having a height of a thickness of the layer of dielectric material. An opening is etched through the buried insulating material at a location away from the dielectric island. An amorphous semiconductor material is deposited to fill the opening through the buried insulating material and to surround the dielectric island. The amorphous semiconductor material is polished until the top surface of the dielectric island is exposed and such that the amorphous semiconductor material surrounds the dielectric island.
A layer of the amorphous semiconductor material is deposited on top of the dielectric island and on top of the amorphous semiconductor material surrounding the dielectric island. The amorphous semiconductor material surrounding the dielectric island and the layer of the amorphous semiconductor material are recrystallized to form a substantially single crystal structure of semiconductor material. The semiconductor material disposed on the dielectric island has a thickness that is less than that of the semiconductor material that extends above the height of the dielectric island to the sides of the dielectric island.
A gate dielectric and a gate electrode of the field effect transistor are formed on top of a thinner portion of the semiconductor material disposed on the dielectric island. A drain extension region and a source extension region are formed by implanting a drain and source dopant into exposed regions of the thinner portion of the semiconductor material disposed on the dielectric island. A channel region of the field effect transistor is formed by the thicker portion of the semiconductor material disposed on the dielectric island between the drain and source extension regions. A drain contact region and a source contact region are formed from the thicker portion of the semiconductor material disposed to the sides of the dielectric island. The drain and source silicides are formed with the drain and source contact regions, respectively.
The present invention may be used to particular advantage when the dielectric island is comprised of silicon nitride (Si3N4) and when the amorphous semiconductor material is comprised of amorphous silicon.
In this manner, the drain and source extension junctions are formed on the thinner portion of the semiconductor material disposed on the dielectric island to minimize short channel effects of the field effect transistor and such that the channel region of the field effect transistor is fully depleted. In addition, the drain and source silicides are formed with the thicker portion of the semiconductor material disposed to the sides of the dielectric island. With thicker drain and source silicides, parasitic resistance at the drain and source of the field effect transistor is minimized to enhance speed performance of the field effect transistor.
These and other features and advantages of the present invention will be better understood by considering the following detailed description of the invention which is presented with the attached drawings.